The present invention relates to a method of making an electrically erasable programmable split-gate memory cell of the type having a control gate and a floating gate wherein the control gate and the floating gate are laterally spaced apart with the floating gate self-aligned to the control gate, and to an isolation in both lateral directions. The present invention further is directed to a cell made by such method.
Electrically erasable programmable split-gate memory cells are well known in the art. One type of such cell has a first and a second spaced apart regions in a semiconductor substrate with a channel therebetween. A floating gate is insulated from the substrate and is over a first portion of the channel. A control gate is insulated from the substrate and is spaced apart from the floating gate and is over a second portion of the channel, different from the first portion. Such a cell is exemplified by U.S. Pat. No. 5,029,130. Methods for making such a type cell is also disclosed in the aforementioned patent.
One of the problems in making such electrically erasable programmable memory cells reliably and reproducibly is the alignment of the floating gate to the control gate and the floating gate to the isolation, in both lateral directions. Such alignment, if it can be accurately and precisely controlled, controls the ultimate size of the cell, which, of course, ultimately determines the density and the yield of the device.
Accordingly, in the present invention, a method of making such an electrically erasable programmable memory cell comprises the steps of providing a first layer of insulating material on a substrate. A first layer of polysilicon is provided on the first layer of the insulating material. The first layer of polysilicon is then patterned, and selective portions removed. A second layer of insulating material is provided on the first layer of polysilicon. The second layer of insulating material is selectively masked and anisotropically removed to define regions in the corresponding first layer of polysilicon which would become the floating gate. The second layer of insulating material is further isotropically etched. The first layer of polysilicon is anisotropically etched to form the floating gate from the first layer of polysilicon. The exposed portions of the first layer of polysilicon is oxidized to form a sharp edge. Silicon dioxide is then deposited on the second layer of insulating material and on the oxidized exposed portion of the first layer of polysilicon. A second layer of polysilicon is deposited on the deposited silicon dioxide. The second layer of polysilicon is anisotropically etched to form the control gate. Such a memory cell would have its control gate and its floating gate self-aligned.